PLL Design from First Principles

A phase-locked loop is one of those circuits that shows up everywhere and is rarely understood deeply. The 1970s TV tuner. The 1990s modem. The 2010s radio base station. The 2020s clock-data-recovery circuit on a serialiser. In every case, it's the same three blocks: a phase detector, a loop filter, a voltage-controlled oscillator. The output is a clean synthesised frequency that tracks a noisy input.

The control-system picture

The three blocks of a PLL map onto the canonical feedback loop:

The phase detector is a subtractor that compares the reference phase to the VCO phase. The loop filter is a controller with proportional and integral terms. The VCO is the plant: its frequency is proportional to the control voltage, so its phase is the integral of the control voltage.

This is the same picture as a PID controller regulating the speed of a motor. The only unusual bit is that the error signal is periodic: phase wraps at 2π, so the linearisation is only valid inside a small region around the lock point. Worth keeping in the back of your mind.

The phase detector: a multiply, in disguise

$$2 \sin(\omega_\text{ref} t + \phi_\text{ref}) \cdot \sin(\omega_\text{vco} t + \phi_\text{vco}) = \cos\!\big((\omega_\text{ref} - \omega_\text{vco})\,t + (\phi_\text{ref} - \phi_\text{vco})\big) - \cos\!\big((\omega_\text{ref} + \omega_\text{vco})\,t + (\phi_\text{ref} + \phi_\text{vco})\big)$$

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The simplest phase detector is a multiplier followed by a low-pass filter. The high-frequency term $\cos\!\big((\omega_\text{ref} + \omega_\text{vco})\,t + \ldots\big)$ is filtered out. What we're left with is $\cos\!\big((\omega_\text{ref} - \omega_\text{vco})\,t + (\phi_\text{ref} - \phi_\text{vco})\big)$. This signal is:

• DC (zero) when $\omega_\text{ref} = \omega_\text{vco}$ and $\phi_\text{ref} = \phi_\text{vco}$, the lock condition
• A slow sinusoid when the frequencies are close but not equal
• A faster sinusoid as the frequency difference grows

So the phase detector's output is really the sin of the phase error, in disguise. To get a clean phase error, the textbook options are:

• A XOR gate for digital square waves (output is a triangle wave around the lock point, linear over ±π/2)
• A Gilbert cell multiplier for analogue signals (true sin of phase error, linear near lock)
• A phase-frequency detector (PFD) for digital signals that may have a frequency offset, with a directional pulse train as its output

The lab uses a PFD-style phase detector, which is the most common choice in modern digital PLLs.

The VCO: integrator by design

A voltage-controlled oscillator's output frequency is a linear function of its input voltage:

$$\omega_\text{vco} = \omega_0 + K_\text{vco} \cdot u_c$$

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The phase is the integral of the frequency:

$$\phi_\text{vco} = \int \omega_\text{vco}\, dt = \omega_0 t + K_\text{vco} \int u_c\, dt$$

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In Laplace notation, the VCO is a pure integrator with gain $K_\text{vco}/s$. This is the plant. The phase detector measures $\phi_\text{ref} - \phi_\text{vco}$, the loop filter amplifies and integrates the result, and the VCO integrates again to produce its phase. Two integrators stacked back to back, which is where the second-order behaviour comes from.

A first-order PLL (no loop filter, just a gain $K$) is a second-order system with one integrator in the controller-free path (the VCO) and another from the phase detector's transfer. The closed-loop transfer function is:

$$H(s) = \frac{\omega_n^2}{s^2 + 2\zeta\omega_n s + \omega_n^2}, \qquad \omega_n^2 = K \cdot K_\text{vco}$$

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That's a second-order system with natural frequency $\omega_n = \sqrt{K \cdot K_\text{vco}}$. With realistic loop-filter damping the ratio tends to land around $\zeta = 0.5$. Underdamped, just barely. A textbook result that surprises nobody who's tuned a control loop.

The loop filter: a P, PI, or PID, by another name

The lab exposes the loop filter as a dropdown. The three options map directly onto the three controllers we already know:

• P (proportional): $F(s) = K_p$. The simplest possible loop. Phase error in steady state is $\Delta\omega / (K_p \cdot K_\text{vco})$, non-zero if the reference frequency is offset.
• PI (proportional + integral): $F(s) = K_p + K_i / s$. The integral term drives the steady-state phase error to zero. This is the workhorse, used in the overwhelming majority of PLLs.
• PID (with derivative): $F(s) = K_p + K_i / s + K_d s$. The derivative term extends the loop bandwidth but amplifies phase-detector noise. Rare in practice for PLLs, because the phase detector's noise is already a problem.

The textbook design problem ("given a reference frequency accuracy, a noise floor, and a settling time requirement, choose K_p, K_i, K_d") is identical to the textbook PID design problem. The same Bode-stability methods, the same trade-off between bandwidth and noise, the same instability when you push the gain too high.

Tracking, lock range, and pull-in

Three concepts in PLL design, often confused:

• Lock range: the range of frequencies the PLL can hold lock on, given that it is already locked. Set by the loop's linear range.
• Capture range is the range of frequencies the PLL can acquire lock on, starting from unlocked. Smaller than the lock range; limited by the loop filter's bandwidth.
• Pull-in range is the range from which the PLL will eventually acquire lock, after a slow transient. Larger than the capture range; set by the loop filter's natural frequency.

Lock Range

Maximum

Holds lock once acquired

Pull-in

Intermediate

Slow transient acquisition

Capture

Minimum

Immediate phase acquisition

The relationships between these three define what the PLL can do in practice. A PLL with a first-order loop filter has all three ranges equal, a degenerate case. A second-order PLL (with PI filter) has capture range < lock range, because the filter's pole at the origin creates a low-pass behaviour during acquisition. A third-order loop (with a narrow filter at high frequency) can have a very wide lock range but a very narrow capture range. In practice you're usually trading one against the other.

The lab: what to look for

The PLL lab at the top of this post is a sandbox for the dynamics described above. Three experiments are worth running:

1. Lock range vs. loop filter type. Switch the filter dropdown between P, PI, and PID. With a small frequency step in the reference, watch the phase error settle. PI gives zero steady-state error; P does not. PID converges faster but with more overshoot.

2. Capture range vs. loop bandwidth. With a chirped reference, the capture range is the maximum chirp slope at which the loop can still acquire. Increase the chirp rate until the loop fails. Notice that increasing K_p extends the capture range but the loop becomes noisier.

3. Stability and gain. Crank K_p up until the loop starts oscillating. This is the conditional stability boundary of a Type-2 system. Reduce K_p until the oscillation just damps. That point is roughly your stability margin.

The same three experiments on a real PLL would take a soldering iron and an afternoon. The lab collapses them into a few clicks.

The PID lab above is the controls-engineering twin of the PLL lab. Same plant, same controller topology, same dynamics.

A PLL is a phase-domain PID controller; a motor drive is a speed-domain PID controller. The mathematics, the design heuristics, the failure modes: they map 1:1.

This isn't a coincidence. The control system is a pattern, and the PLL is one of its many instantiations. Once you've got the pattern, you can recognise it everywhere.

Why this post exists

The PLL is the canonical example of a feedback control system operating on a non-electrical variable. A PID controller regulates a motor speed. A PLL regulates a phase. The pattern is the same; the application is different.

The lab at the top is a working sketchpad for that pattern. Drag the controls, watch the dynamics, observe the regimes (locked, slipping, unlocked) emerge from the same equations. The PID lab in "The lab: what to look for" is the controls lab: the same Bode plot (from "The loop filter: a P, PI, or PID, by another name"), the same design rules, a different physical system. The same loop, twice.

The two labs are the most direct demonstration I know of the transfer function as a unifying concept in modern engineering: once you can read a Bode plot, you can design a PLL, a PID, a state-space observer, a Kalman filter. The transfer function is the language, and the labs are where we get to have the conversation. Go break one and see what falls out.

Reading further

• Gardner, Phaselock Techniques, 3rd ed. (2005) is the canonical reference, dense but complete. Chapter 1 is a one-paragraph summary; chapter 2 is the maths; chapter 6 is the loop filter design.
• Best, Phase-Locked Loops: Design, Simulation, and Applications, 6th ed. (2007): more accessible, better for engineers who want to build one.
• Abramovitch, Phase-Locked Loops: A Control Centric Tutorial (2002) is free online. The clearest treatment of the control-system picture, written by a controls engineer for controls engineers.
• Franklin, Powell, Emami-Naeini, Feedback Control of Dynamic Systems, 8th ed. (2019), chapter 8: phase-locked loops as a control-system application. The reason a PLL feels familiar if you've read a controls textbook.